8051 external ram(62256) and also using address & data lines as GPIO

Question

My application requires 8051 with external RAM 32K(62256) I plan to use one chip(62256) to address 32k, and I want to use the other 32K to access GPIO like higher 32k goes to RAM & lower 32k to keypad and other GPIO peripherals is this possible to do so?

Answer 1

Yes, it's possible. In this particular case, it's even pretty simple/easy.

You're splitting the address space in half. When you address the lower half of the address space, A15 will be low. When you address the upper half, A15 will be high.

The 62256 has an active low chip-enable pin (CE#), meaning the chip is enabled only when CE# is low. You want to enable the 62256 only when A15 is high, so you'll connect A15 on the 8051 to an inverter, and from there to CE# on the 62256.

Although you haven't described the other chips in any real detail, the same basic idea applies with them--you wire up logic that enables each chip if and only if the address is in the correct range. For example, let's say you have some peripheral that looks to the processor like 256 bytes of memory. To keep things really simple, let's assume this peripheral has an AD0 through AD7 that it uses for addresses and data, and uses the same bus cycles as an 8051.

Since you want the CPU to see that chip in the first 256 bytes of the address space, that means it should be active only when all the higher address lines (A8 through A15) are low. So, we feed them into an 8-input OR gate, so its output is high if any of its inputs are high.

So, as a starting point, your decoding circuitry would look vaguely like this:

This is just a sketch though. Just for example, you'll also need circuitry for the OE# pin on the 62256, which will be activated by the WR# pin on the 8051, and unless the bus cycles for the other chips happen to match perfectly with those for the 8051, you'll end up with (for example) some buffers to hold data coming from one until it's time to send it to the other.