Am I doing the 5-cycle Pipeline Clock Diagram with Stalls and Forwarding in a right way?

Question

There is a set of instructions in the following sequence,

  1. lw $s2,0($s1)
  2. lw $s1,40($s6)
  3. sub $s6,$s1,$s2
  4. add $s6,$s2,$s2
  5. or $s3,$s6,$zero
  6. sw $s6,60($s1)

I must create a pipeline clock diagram for implementation with stalls and all-forwarding (Mem-Exe, Exe-Exe, WB-Exe).

[Fig: The Diagram I created.] (https://i.stack.imgur.com/KZO5b.png)

I did one stalling for each instruction (when required). When I see most of the solved examples, they tend to perform two stalling. For example, in the **sub $s6, $s1, $s2 ** column, I have just used 1 NOP(Stall) in CC5 since $s2 can be forwarded to EXE from WB (of the first instruction), and also $s1 to EXE from Mem/WB reg (of the second instruction). Similarly, I don't see any other visible data hazard.

Please correct me if I am wrong! I am a beginner in computer architecture and need your help!

Answer 1

You are correct, there's a stall required between 2 & 3 because of the RAW on $s1 — a MEM->EX forward will be used; the stall is for EX on 3.

After that, this same stall bubbles through the pipeline.

However, for the sw instruction, you've both delayed the start (IF) and also inserted a NOP.  Both of these are not necessary.  There is a RAW hazard between 4 & 6 on $s6 but that is handled with a forward.

In this case the forward can be from WB(instr #4.)->MEM(#6.), or from MEM(#4.)->EX(#6.).  Store is an interesting instruction, having two register source operands, but only the base address register operand is required in EX for addition of the addressing mode computation, whereas the other, the value to store, isn't actually needed until MEM.

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I like this way of showing bubbles.  Here in this different example, only one stall exists between 1st and 2nd instruction, the rest can run full speed.

IF  ID  EX  MM  WB                          load instruction
    IF  ID  --  EX  MM  WB                  use of load, stall in EX waiting for MM
        IF  --  ID  EX  MM  WB              stall b/c prior instruction stalled
            --  IF  ID  EX  MM  WB          stall b/c a prior instruction stalled
                    IF  ID  EX  MM  WB      bubble finally gone
                        IF  ID  EX  MM  WB 

The -- indicates the bubble where the stage shown after executes, yet needs to be repeated as the later stage is busy and cannot take up the work.  In -- EX that means that EX was busy holding that instruction in the -- but had to be repeated almost as if EX EX.  Same for the others.

To be clear, I think that stalling in ID as you're diagraming also works.