BDC to 7-segment decoder missing VCD file

Question

When I run this code to EDAplayground, it will give me an error of:

Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

//Verilog module.

module segment7(bcd,seg); 

        input [3:0] bcd;
        output [6:0] seg;
        reg [6:0] seg;
    always @(bcd)
    begin
        case (bcd) //case statement
            0 : seg = 7'b0000001;
            1 : seg = 7'b1001111;
            2 : seg = 7'b0010010;
            3 : seg = 7'b0000110;
            4 : seg = 7'b1001100;
            5 : seg = 7'b0100100;
            6 : seg = 7'b0100000;
            7 : seg = 7'b0001111;
            8 : seg = 7'b0000000;
            9 : seg = 7'b0000100;
            
            default : seg = 7'b1111111; 
        endcase
    end
    
endmodule

Testbench:

module tb_segment7;

    reg [3:0] bcd;
    wire [6:0] seg;
    integer i;

    segment7 uut (.bcd(bcd), .seg(seg));

    initial begin
        for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
        begin
            bcd = i; 
            #10; //wait for 10 ns
        end     
    end
endmodule

Answer 1

Add this initial block to the testbench, to load the files needed for viewing waves.

module tb_segment7;

  // other stuff

  // add me
  initial
    begin
      $dumpfile("dump.vcd"); 
      $dumpvars;
    end
  
endmodule

See loading waves

Alternatively, Uncheck the "Open EPWaves after run" box, remove $dumpfile and $dumpvars, and use $monitor to print variables to instrument (instead of using waves). The $monitor statement prints when there is a change on its arguments.
Like this:

module tb_segment7;

  // more stuff
    
  // 
  //initial
  //  begin
  //    $dumpfile("dump.vcd"); 
  //    $dumpvars;
  //  end
  
  // add me instead
  initial
    $monitor("bcd=%h, seg=%h",bcd,seg);
  
endmodule

Which produces the output:

bcd=0, seg=01
bcd=1, seg=4f
bcd=2, seg=12
bcd=3, seg=06
bcd=4, seg=4c
bcd=5, seg=24
bcd=6, seg=20
bcd=7, seg=0f
bcd=8, seg=00
bcd=9, seg=04
bcd=a, seg=7f
bcd=b, seg=7f
bcd=c, seg=7f
bcd=d, seg=7f
bcd=e, seg=7f
bcd=f, seg=7f