build a 8bit ALU using verilog

Question

I'm trying to build an 8bit datapath in an ALU that can add, sub, OR, AND two operands.

I want to use a case statement for each of the operations in the code but I keep getting error messages.

This is what it looks like so far:

    module alu (
      input     [7:0] xa,xb,
      input     [7:0] op_sel,
      input wire ctrl,
      output reg    0Zero, 0Carry,
//0Zero infers latch: can only be assigned to 1/ always reg
      output reg [7:0] result_out,
      );
    always @(*)
    8'hE0 :
    //4 bit for now
        begin
            out = 8'b0;
            0Carry = 1'b0;
            //calculate value
                    case (1) //alu controlled by ctrl signal
                        8'hA0: out = xa&xb;
                        //
                        8'hB0: (0Carry ,out) = xa+xb;
                        //
                        8'hC0: (0Zero , 0Carry, out) = xa-xb;
                        //
                        8'hD0: out = ~(xa|xb);
                        //
                    endcase
                end

Answer 1

Your case expression is 1, you should change that into some variable. Here is an example case statement:

reg [1:0] address;
case (address)
  2'b00 : statement1;
  2'b01, 2'b10 : statement2;
  default : statement3;
endcase

If the address value is 2'b00 then statement1 will be executed. Statement2 is executed when address value equals 2'b01 or 2'b10. Otherwise statement3 is executed.