Cache coherence- MESI protocol

Question

Can there be a case in a cache employing a MESI protocol (has l1 and l2 inclusivity employed) where l2 can send an invalid instruction to an already invalid line in l1.

Answer 1

An "invalidate request", you mean?

I guess so, if L2 doesn't filter its requests according to what it knows about L1, it might just always send an INVD to L1 every time it evicts a line. No idea if this is plausible for a real design. (Eviction from L2 could be caused by a HW or SW prefetch into L2, rather than in response to L1 write-back.)

Or if the CPU core can invalidate a line in L1 at the same time that L2 is sending an invalidate, the INVD could arrive in L1 after it's already invalidated the line.

Answer 2

There could be a scenario where the L2 simply does not know if the L1 has the line, because the L1 is allowed to silently drop it.

In fact, if the L2 is inclusive, there's hardly any reason to waste bandwidth when evicting a non-modified line from the L1 (capacity eviction), because the L2 already has a copy and there's no change. It is therefore likely that many lines in the L2 are still there long after they were evicted from the L1. An eviction from the L2 when it finally arrives (later, since it's bigger) would have to send back a snoop to enforce inclusiveness, because it can't be sure if the line is still in the L1 or not.