Can I implement Branch target buffer in two stage pipelined RISC architecture?

Question

I am trying to implement the BTB in low-level microcontroller such as PIC16. I don't know is it feasible or not. So wanted your suggestion.

Thanks.

Answer 1

The basic BTB is fairly simple, and is the equivalent of

BTBEntry be = BTB[curAddr & BTBBitMask];
nextFetch = be.addr;

which implemented as electronics takes the lower curAddr bits and feed them into a BTB memory and get the next address out.

And when the branch is resolved the result is written back into the BTB.

The lookup can be done in parallel with memory fetch and must be faster as additional steps must be done.

struct BTBEntry {
  int addr;
  int curAddr; // upper address bits.
}

To not just jump random around in the program due to the addr stored not corresponding to the curAddr, we also need to check if the address we are looking up is for the correct branch.

if ((curAddr & ~BTBBitMask) == be.curAddr)
  nextFetch = be.addr; // found in the BTB
else
  nextFetch = curAddr + instrutionSize; // not found, take next instruction

So it can be done, if the BTB is small enough and the total time used is less than an instruction fetch. But the effect might not be so large as you might want.