Defining different parameter value for simulation and synthesis

Question

I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000;). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using ModelSim). For example I would like something like:

if(IN_SIM) begin
parameter SPI_RATE = 2_000_000;
end
else begin
parameter SPI_RATE = 1_000_000;
end

Thanks!

Answer 1

Yes, that's possible. SystemVerilog supports conditional compiler directives such as `ifdef, `ifndef, `else, `elsif, and `endif. Note that those directives are using a grave accent (ASCII 0x60) and not a normal apostrophe (ASCII 0x27).

Furthermore, most synthesis tools support the macro identifier SYNTHESIS. So, you could do the following:

`ifdef SYNTHESIS
  parameter SPI_RATE = 1_000_000;
`else
  parameter SPI_RATE = 2_000_000;    
`endif 

Answer 2

Yes. You can set a macro from the command line in any simulation using the +define plusarg, eg:

+define+SPI_RATE=2_000_000

Then somewhere in your code, you can say

parameter SPI_RATE = `SPI_RATE;

And in your synthesiser there will be a mechanism for setting the value of a macro: read the instructions for your synthesiser.

Answer 3

With Synplify Pro, you can use the /*synthesis translate_off */ /*synthesis translate_off */ to accomplish this, a similar construct is usable in VHDL with appropriate syntax/comment changes. Xilinx Vivado uses // synthesis translate_off and // synthesis translate_on

const logic IN_SIM = 1'b0
/*synthesis translate_off */
    || 1'b1
/*synthesis translate_on */
    ;

The advantage of this construct is that it doesn't require any external scripting changes.

Answer 4

IMHO -

Using the first answer

`ifdef SYNTHESIS

is much preferred over the 3rd answer

/* synthesis translate_off */

The last form is a variation of /* synopsys translate_off */, which was unique to one synthesis tool.

The macro SYNTHESIS has been in common use for more than a decade, and should be defined by any synthesis tool, without any extra command line options.

If you want to run equivalence checking (rtl vs gate level netlist), you will probably need to define the SYNTHESIS macro by the method recommended for that equivalence tool.