Generate specific clock slow down the simulation

Question

I have to generate multiple clock in my top (testbench).

The simulation ran ok until I added the following code:

   initial begin
      tb_pcie_clk_q0p = 1'b0;
      forever begin
     #5ns;  //100MHz (half cycle)
     tb_pcie_clk_q0p = ~tb_pcie_clk_q0p;         
      end      
   end
   assign tb_pcie_clk_q0n = ~tb_pcie_clk_q0p;

In addition I have already had other clocks like:

   initial begin
      tb_fpga_clk = 1'b0;
      forever begin
         #4ns; //125 MHz
         tb_fpga_clk = ~tb_fpga_clk;
      end
   end

 assign tb_clk = dut.clk_rst_ctrl_i.clk_250;  

Answer 1

I am not sure how much your simulation slows down exactly from your comment but I would imagine new clock would exercise more codes in your design and test bench which would impact the simulation performance. I think most of simulator supports to generate simulation profile so you can analysis which portions of code slows down.