How do I create and use a Task in Verilog

Question

I have recently been playing with the Arduino MKR Vidor 4000, and I have run into a small problem. I want to be able to reuse code (like with a function in C++) and have the defined variables local to the piece of code, so they don't interact. I have come across Tasks in Verilog, and these seem to be the correct way of doing this.

The problem is, I can't get Quartus to compile it. It just reports an error:

Error (12006): Node instance "comb_6" instantiates undefined entity "test". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

Here is my code:

task automatic test(input [3:0] in, output [3:0] out);
   reg [3:0] temp;
   assign temp[0] = in[0];
   assign out[0] = temp[0];
endtask
test(bMKR_D[4:1], bMKR_D[8:5]);

This is included by a file which defines the available MKR Vidor pins.

Edit: Here is a minimal reproducible example... I think

module MKRVIDOR4000_top
(
  // Input definitions available for the MKR Vidor 4000
);
// Other signal declarations

// My code
task automatic test(input [3:0] in, output [3:0] out);
    reg [3:0] temp;
    assign temp[0] = in[0];
    assign out[0] = temp[0];
endtask
test(bMKR_D[4:1], bMKR_D[8:5]);

endmodule

From what I gather from the comments, I shouldn't be using any assigns inside a task. And I should also only call tasks from inside an always/begin-end/initial etc. If I can't use tasks this way, what should I do to create reusable code in order to make basic logic gates, that can be synthesised? E.g a register bank

Answer 1

I have put the code I wanted to be able to reuse in a module, and it works okay now! I am not sure if this is what I should be doing, so if anyone has a better way to do it, then I'm all ears!

I have, effectively, done this:

module test (input [3:0] in, output [3:0] out);
reg [3:0] temp;
assign temp[0] = in[0];
assign out[0] = temp[0];
endmodule

module main;
reg [7:0] bMKR_D;
test test1 (bMKR_D[4:1], bMKR_D[8:5]);
endmodule