As the title says, what can be the possible boolean expression of the logic circuit given? The Truth table is also included.Logic Circuit
I have tried to solve my own Boolean Expression and coded it into verilog but I don't think it's correct.
As the title says, what can be the possible boolean expression of the logic circuit given? The Truth table is also included.Logic Circuit
I have tried to solve my own Boolean Expression and coded it into verilog but I don't think it's correct.
The identification of a simplified boolean expression from a table is a use case for a Karnaugh_map which is an analysis method for simplifying boolean expressions.
Here is the K-map and resulting simplification for the table in the question:
The K-map is a typical engineer interview question so it's valuable to understand and also valuable as an analysis tool. Its not used in HDL/Verilog design as much because synthesis tools perform simplification/logic reduction.
Alternatively, a table can be implemented in Verilog as a ROM without simplification. The tools will simplify it. Simplifying expressions can make them harder to read in Verilog code (the opposite of what to do), which is another reason not to use K-maps most of the time when writing Verilog code.
module decoder_rom (
input wire a,
input wire b,
input wire s0,
input wire s1,
//
output reg y
);
always @*
case ( { a, b, s0, s1} )
4'b0000:
y = 0;
// more rows
4'b0100:
y = 1;
// more rows
4'b1111:
y = 0;
default:
y = 0;
endcase
endmodule
The truth table appears to describe
a XOR b
.Regardless of the values of
s0
ands1
, iff eithera
is true orb
is true (not both), theny
is true.