How does 'event' works?

Question

I'm studying SystemVerilog event data types. But I can't understanda the simulation results.

How does event works in SystemVerilog?

UPDATE

1 module events();
  2 // Declare a new event called ack
  3 event ack; 
  4 // Declare done as alias to ack 
  5 event done = ack; 
  6 // Event variable with no synchronization object
  7 event empty = null; 



  9 initial begin
 10    #1  -> ack;
 11    #1  -> empty;
 12    #1  -> done;
 13    #1  $finish;
 14 end
 15 
 16 always @ (ack)
 17 begin
 18   $display("ack event emitted");
 19 end
 20 
 21 always @ (done)
 22 begin
 23   $display("done event emitted");
 24 end
 25 
 26 /*
 27 always @ (empty)
 28 begin
 29   $display("empty event emitted");
 30 end
 31 */
 32 
 33 endmodule

How does it show as following?

 ack event emitted
 done event emitted
ack event emitted <== I don't understand here Why does it happens?
 done event emitted

I think that it should be like this.

 ack event emitted

 done event emitted

 done event emitted

Answer 1

I think you may be confused about why the events are printed multiple times? Have a look at line5:

event done = ack;

Now ack and done are synonymous with each other, whenever one event is triggered the other is as well, since each is triggered once you get 4 printouts.