how is 'stream ID' or 'iommu specifier' determined in PCIe root complex mode?

Question

This is from Documentation/devicetree/bindings/pci/pci-iommu.txt (linux-5.10.0)

PCI root complex
================

Optional properties
-------------------

- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
  data.

  The property is an arbitrary number of tuples of
  (rid-base,iommu,iommu-base,length).

  Any RID r in the interval [rid-base, rid-base + length) is associated with
  the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).

- iommu-map-mask: A mask to be applied to each Requester ID prior to being
  mapped to an IOMMU specifier per the iommu-map property.


Example (1)
===========

/ {
    #address-cells = <1>;
    #size-cells = <1>;

    iommu: iommu@a {
        reg = <0xa 0x1>;
        compatible = "vendor,some-iommu";
        #iommu-cells = <1>;
    };

    pci: pci@f {
        reg = <0xf 0x1>;
        compatible = "vendor,pcie-root-complex";
        device_type = "pci";

        /*
         * The sideband data provided to the IOMMU is the RID,
         * identity-mapped.
         */
        iommu-map = <0x0 &iommu 0x0 0x10000>;
    };
};

I can't understand the meaning of Any RID r in the interval [rid-base, rid-base + length) is associated with the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base). I understand this iommu-map specifies the relationship between the master device (requesting transaction from the PCIe bus to this root complex) and the assigned iommu for the device. This example says, rid 0 ~ 0x10000 is assigned to iommu specifier 0 ~ 0x10000. The document says rid is formed by {bus,device,function} (16 bits).
How is this single number iommu specifier determined by the PCIe core device? Is it device dependent(with the driver's settig)? In arm64 case, the smmu-v3(arm's type of iommu) needs stream ID (and substream ID which is mapped from PASID in PCIe TLP) and when this #iommu-cells is 1, I don't know how this stream ID is passed from the PCIe core device to smmu-v3. If anyone could clarify it, it would be much grateful.