How should I define the size of L3 cache in Gem5?

Question

I had working code that implemented a two level cache in Gem5. I wanted to add a third level, so I added this to my caches.py code:

#make L3 cache
class L3Cache(Cache):
#tags = FullyAssoc()
size = '256kB'
assoc = 1
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12

#pass options into cache
def __init__(self, options=None):
super(L3Cache, self).__init__()
if not options or not options.l3_size:
return
self.size = options.l3_size

#function to connect memory-side to CPU-side bus
def connectCPUSideBus(self, bus):
    self.cpu_side = bus.mem_side_ports

def connectMemSideBus(self, bus):
    self.mem_side = bus.cpu_side_ports

This is how I connected the caches together in three_level.py

#create L1 caches
system.cpu.icache = L1ICache(options=options)
system.cpu.dcache = L1DCache(options=options)

#connect L1 cache to CPU ports
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)

#use helper function to connect L1 cache to L2 cache and L3 cache
system.l2bus = L2XBar()
system.l3bus = L2XBar()

system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

#create L2 cache
system.l2cache = L2Cache(options=options)
system.l2cache.connectCPUSideBus(system.l2bus)
#system.membus = SystemXBar()
#system.l2cache.connectMemSideBus(system.membus)

#create L3 cache
system.l3cache = L3Cache(options=options)
system.l3cache.connectCPUSideBus(system.l3bus)

#create memory bus
system.membus = SystemXBar()

#connect to memory side
system.l2cache.connectMemSideBus(system.membus)
system.l3cache.connectMemSideBus(system.membus)

And this is the error I get when I try building three_level.py

command line: build/X86/gem5.opt configs/tutorial/part1/three_level.py

Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
src/mem/dram_interface.cc:690: warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
src/base/statistics.hh:279: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
system.remote_gdb: Listening for connections on port 7000
src/mem/coherent_xbar.cc:140: warn: CoherentXBar system.l3bus has no snooping ports attached!
src/base/statistics.hh:1175: fatal: fatal condition (_x <= 0) || (_y <= 0) occurred: Storage sizes must be positive
Memory Usage: 621924 KBytes

I am guessing there is some sort of memory constraint that is holding me back, but I got the same error when I set the size of L3 to 16 kB instead. Where is the root of the issue?

Answer 1

I see one major problem with your configuration, not sure this is the source of current error but if not, this surely will create new error down the line. I'm assuming you want to memory hierarchy as such : L1 -> L2 -> L3 -> MainMemory . ( L2 ask L3 if cache miss happen and L3 ask main memory if cache miss happen ). Now you connected your L2 memory side port to system memory bus instead of L3bus. Thus your request will not go to L3. You also connected L3 cpu side port with L3bus. Thus any snoop request generated at L3bus have no connection to upper level to snoop resulting this warning:

src/mem/coherent_xbar.cc:140: warn: CoherentXBar system.l3bus has no snooping ports attached!

Second probable issue how you initialized the size. I have not seen cache size definition with small K (kB). Try replacing "size = '256kB' " with " size = '256KiB' ". May be gem5 is not parsing kB exactly the way you want it to be.