For Intel I use:
mov, eax, 2h
cpuid
it gives "descriptor decode value" - ok;
For AMD I use:
mov, eax, 80000005h
cpuid
It gives associativity and entries for 4MB in eax (4KB in ebx).
Here it is :
EAX = FF30FF10 EBX = FF30FF20" FF - full assoc. data, 48d entries data, FF - full assoc. instr, 16d entries instr
So I have both 4KB and 4MB or what?
P.S. i`m right that TLB page and L1 cache - different things? Or maybe L1 instr. cache size is what I need?
This entry on wikipedia may help you clear up some of the confusion on the different TLB sizes. It's under the heading "Multiple TLB's":