I am creating a DSP application using the RP2040, an I2S ADC and an I2S DAC. One of the primary requirements is low latency, the second is efficient usage of the CPUs to calculate the actual DSP algorithm.
I2S input and output is implemented using one PIO state machine each. Both ADC and DAC run at the same sampling rate (i.e. the clock dividers in the two PIO state machines are set to the same values). The DSP algorithm requires a certain amount of samples past the newest one. Therefore, for the input data I chose to use a ring buffer which is filled via DMA from the ADC.
My question is: how should I push the processed samples to the output?
My ideas so far are:
One possible way of implementing this would be to push every processed output sample to the DAC's PIO TX-Queue. This push would block when the queue is full and thus provide a convenient synchronization point for the algorithm. Is this an efficient way to implement this?
Would it be better to also use DMA for the I2S output? My thinking is that this way I would need to fill a certain amount of samples into an output buffer before it can be sent via DMA, which would increase latency. Also, my algorithm would need to somehow actively wait if it was faster than the input and output. Is there a way to implement this double DMA method so that it becomes more efficient in terms of CPU usage than the one with the blocking push? If so, how can the latency increase be mitigated?
Is there another even better way to implement this kind of application?