how to port the threadX RTOS on the cortex R5?

Question

I tried to port Threadx RTOS to the cortex-R5 of the zynq UScale+.

• I copied the port directory corresponding to the R5 and the common Threadx .h and .c files into my example code tree.

• I defined the Include path to point to the directory where the Azure RTOS Threadx header files are located.

• I did the same for the .c files directory files

Image showing the inclusion of the header file path in the application tree structure in Vitis IDE:

But when I compile I get one of the errors from the assembler code files

undefined reference to `__tx_fiq_processing_return'

occurs in the tx_thread_fiq_context_save.S files

#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@    /* Call the ISR enter function to indicate an ISR is executing.  */
@
    PUSH    {lr}                                @ Save ISR lr
    BL      _tx_execution_isr_enter             @ Call the ISR enter function
    POP     {lr}                                @ Recover ISR lr
#endif

    B       __tx_fiq_processing_return          @ Continue FIQ processing 
@
__tx_thread_fiq_not_nested_save:
@    }  
@

And

undefined reference to `_sp'

occurs in the tx_initialize_low_level.S files.

    .global _tx_initialize_low_level
    .type   _tx_initialize_low_level,function
_tx_initialize_low_level:
@
@    /* We must be in SVC mode at this point!  */
@
@    /* Setup various stack pointers.  */
@
    LDR     r1, =_sp                            @ Get pointer to stack area

but I can't find the file where its symbols were defined, unless I'm installing it incorrectly. please, i'd like to have proposals for a solution to port Threadx to the cortex-R5.