How to solve the issue found in the error log of ltspice?

Question

I am trying to simulate Buck converter LM536005-Q1 in ltspice. I have imported third party module of LM53600-Q1 from TI website. I have created symbol and stated running simulation but I did not get the waveform window. When I check the log, I am getting following error enter image description here

The simulated circuit is attached here enter image description here

The link for the third party model downloaded is given here https://www.ti.com/product/LM53600-Q1?keyMatch=LM536005&tisearch=Search-EN-everything#design-development##design-tools-simulation

I am not getting how resolve this issue. Somebody please help.

Answer 1

I don't know what is the purpose of the IC, but I think your problem is with the schematic capture.

If you try the simulation via spice code (create an empty file and open it with LTSpice) you can at least simulate. I tested the code below it I've got the result in the figure.

I don't know if the results make any sense. That's up to you. But with the code you can at least to simulate and test some parameters. I simulated only 1.2 ms because it was costing me the whole processing power and took about 10 min for that.

Important to notice that:

1. The simulations of power electronic circuits are really time (and processing) consuming;
2. So I suggest you to modify these parameters inside Control Panel:
   • Compression: unmark everything;
   • Spice: use Alternate solver, set the max threads possible and thread priority to high;
   • Operation: unmark Marching Waveforms. With it LTSpice keeps trying to calculate and show you something. If you unmark it, LTSpice will calculate everything and only show you something in the end. I know the curiosity if the simulation is going towards the point you want is very high, but the computation is considerably faster this way.
3. Because of 1, I also set and used the initial conditions for the voltage of the nodes with capacitors attached to and the inductor current.
4. And, also because of 1, I don't recommend you to set a time step for your simulation: let LTSpice decide it for you. Its convergence power is its best of its characteristics.

** Test Simulation
** options and includes
.include LM536005-Q1_TRANS.lib

*** Circuit
** Your IC Terminals from .lib file
** AGND BOOT ENABLE FB GND PAD RESET_N SW SYNC_MODE VCC VIN
** The connections
* x is the spice letter for subcircuits
* see the .subckt entry in .lib for details
x1 gnd boot vin fb gnd gnd RESET_N sw gnd vcc vin LM536005-Q1_TRANS
** Passive components
c1 vin gnd 10u
c2 boot sw 100n
l1 sw fb 4.7u
c3 fb gnd 10u
c4 fb gnd 10u
c5 fb gnd 10n
c6 vcc gnd 1u
** Sources
v1 vin gnd dc 12
i1 fb gnd dc 0.5

** Initial Conditions for some important
** nodes and elements
.ic v(fb)=-180m i(l1)=0.5 v(sw)=-180m

** Analysis with Initial Conditions
.tran 1 uic

.end

[Output - overall][1]