How to use explicit addressing in IBM (HLASM)

Question

I’ve been looking for information about explicit addressing, online but there is nothing and there is, the explanations are pretty vague. I hope someone can explain me with details and if possible witn example. I would like to know, what registers should be used as index, base, and what should be the displacement value

Example 8(,4) or 5(0,5) or 6(7)

Answer 1

It can depend on the instruction being executed. Please see this reference from IBM to help sort through the details. Being an old Z performance person when people ask a question about performance the answer is almost always, “It depends”

See this article

Registers that are not explicitly coded in symbolic assembler language representation of machine instructions, but are nevertheless used by assembled machine instructions, are divided into two categories: Base registers that are implicit in the symbolic addresses specified. (See Addresses.) The registers can be identified by examining the object code or the USING instructions that assign base registers for the source module.

Registers that are used by machine instructions, but do not appear in assembled object code. For double shift and fullword multiply and divide instructions, the odd-numbered register, whose number is one greater than the even-numbered register specified as the first operand.

For Move Long and Compare Logical Long instructions, the odd-numbered registers, whose number is one greater than even-numbered registers specified in the two operands.

For Branch on Index High (BXH) and the Branch on Index Low or Equal (BXLE) instructions, if the register specified for the second operand is an even-numbered register, the next higher odd-numbered register is used to contain the value to be used for comparison.

For Load Multiple (LM, LAM) and Store Multiple (STM, STAM) instructions, the registers that lie between the registers specified in the first two operands.

For extended-precision floating point instructions, the second register of the register pair.

For Compare and Form Codeword (CFC) instruction, registers 1, 2, and 3 are used. > For Translate and Test (TRT) instruction, registers 1 and 2 are used. For Update Tree (UPT) instruction, registers 0-5 are used.

For Edit and Mark (EDMK) instruction, register 1 is used. For certain control instructions, one or more of registers 0-4 and register 14 are used. See "Control Instructions" in the applicable z/Architecture Principles of Operation manual.

For certain input and output instructions, either or both registers 1 and 2 are used. See "Input/Output Instructions" in the applicable z/Architecture Principles of Operation manual. On a processor with a vector facility:

1. For instructions that manipulate long floating-point data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.

2. For instructions that manipulate 64 bit signed binary data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.