I want to add a checker that checks if clk is toggling when enable is '1'. The frequency of the clk is random (unknown)

Question

Let's say we have a signal named "clk" and we want to make sure that clk toggles when "enable" is '1'. And the frequency of the "clk" is not known.

Answer 1

How about this?

module top();
  
  reg clk;
  reg enable;
  
  always @(posedge enable)
    begin
      automatic bit toggled=1'b0;
      automatic process p;
      
      fork
        begin
          p = process::self();
          $display("%t expecting CLK toggle ...", $time);
          @(clk) toggled = 1'b1;
          $display("%t CLK toggled!", $time);
        end
      join_none
      
      @(negedge enable);
      if (!toggled) $error("CLK not toggled!");
      p.kill();
    end
  
  initial
    begin
      
      clk = 1'b0;
      enable = 1'b0;
      $dumpfile("dump.vcd"); $dumpvars;
      
      repeat(3)
      begin
        #5;
        enable <= 1'b1;
        #5;
        clk <= ~clk;
        #5;
        enable <= 1'b0;
      
        #5;
        enable <= 1'b1;
        #5;
        //clk <= ~clk;
        #5;
        enable <= 1'b0;
      end
      
      #5;
      $finish();
      
    end
  
endmodule : top

Answer 2

I think what you need here is some kind of clock gating where we will create a version of the clock that doesn't start toggling except when the enable in high a block diagram of that block is as follows

For that if you have a standard cell there are cells that is used for that you can use one of them in your code in case you don't have it here is the following RTL to describe the circuit above

module latch(clk, in, out);
  
  
  input clk, in;
  output reg out;
  
  
  always@(*) begin 
    if(clk) begin
        out <= in;
    end
  end
  
  
  
endmodule


module clk_gate(clk_in, en, clk_out);
  
  input clk_in;
  input en;
  output clk_out;
  
  wire latch_out;
  
  latch u1 (.in(en), .clk(~clk_in), .out(latch_out)); 
  and u2 (clk_out, latch_out, clk_in);
  
  
  
endmodule

and here is the testbench for this circuit

`timescale 1ns/1ns
module tb();
  
  wire out;
  wire clk_out;
  reg in, clk, en;
  always #5 clk = ~clk;
  
  latch DUT_latch( .clk(clk), .in(in), .out(out));
  clk_gate DUT_clk_gate( .clk_in(clk), .en(en), .clk_out(clk_out));
  
  initial begin 
    $dumpfile("dump.vcd");
    $dumpvars(1);

    clk = 0;
    in = 0;
    en = 0;
    #7
    in = 1;
    en = 1;
    #3
    in = 0;
    en = 0;
    #8
    in = 1;
    en = 1;
    
    #100
    $stop;
  end
  

  
  
endmodule

Where clk_out is the gated version of the clock which is enabled only when the enable is 1 now you can used that version of the clock whenever you want instead of the original clock Note: out is the output of the latch and clk_out is the output of the clock gating circuit