icarus verilog specify delays not respected if there are conditionals

Question

Trying to model a 74245 with delays representative of the HCT device.

I am finding that the timings I'm providing in a specify block are not respected.

I have added an extra route A->C (not part of my orig design) to illustrate that the delays can work, just not where there are conditionals in the expression ie none of the other delays are effective.

If I put a delay inline on the assign then this is always respected.

My code is here : https://www.edaplayground.com/x/hDa

Any ideas?

I am a noob.

Answer 1

It was an icarus bug and it's just been fixed on master. https://github.com/steveicarus/iverilog/issues/315#issuecomment-607800126

Thanks all