Is default value required for a Verilog parameter declaration?

Question

Parameters in Verilog code is usually declared with a default value, like:

parameter UP = 1;

But if the parameters is always to be overridden at module instantiation, then I have also seen declaration without default value, like:

parameter UP;

This parameter declaration without default value can compile in ModelSim, but fails compilation in Riviera-PRO.

The Verilog IEEE Std 1365-2005 section "4.10.1 Module parameters" shows that default value is required (not optional), as:

So either ModelSim is forgiving by accepting a parameter without default value if default value is required, or Riviera-PRO lacks support for parameters without default value if default value is optional.

Thus: Is default value required for a Verilog parameter declaration?

---

A counter module is included below, including parameter declaration without default value, for reference.

module counter
  (
   input            clk,
   input            rst,
   output reg [3:0] cntr
   );

   parameter UP;

   // Counter
   always @(posedge clk or posedge rst)
     begin
        if (rst)
          cntr <= 4'd0;
        else
          if (UP)
            cntr <= cntr + 1;
          else
            cntr <= cntr - 1;
     end

endmodule

---

A testbench with using the counter is also included below for reference:

module testbench();

   // Declarations
   reg clk;
   reg rst;
   wire [3:0] cntr;

   // Clock generation
   initial begin
      clk = 0;
      forever #5 clk = ~ clk;
   end

   // Reset generation
   initial begin
      rst = 1;
      #100;
      rst = 0;
   end

   // DUT counter
   counter #(.UP(1)) dut (clk, rst, cntr);

endmodule

Answer 1

All verilog standards leave a room for interpretation. Also note that 1394 was last updated in 2005 and is not active any longer. It is superseded by the SystemVerilog standard.

Default value is required according to your quote from 1394 standard. If ModelSim ignores it, then the tool is in violation of the standard. You can report it to Mentor. However, this behavior could be intentional due to the historical reasons or some technical reasons.

In your case, this interpretation of the standard does not affect behavior of user program (assuming that the parameter is always overwritten).

It is known that multiple vendors interpret and/or implement standard differently. There are multiple violations. Some they refuse to fix due to the customer base which could have used those violations in their code.

The System Verilog standard has a clarification and allows to omit the value but only in the port parameter declarations:

param_assignment ::= parameter_identifier { unpacked_dimension } [ = constant_param_expression ] ^18

^18) It shall be legal to omit the constant_param_expression from a param_assignment or the data_type from a type_assignment only within a parameter_port_list. However, it shall not be legal to omit them from localparam declarations in a parameter_port_list