Is it possible to use the same expression in a case statement included in different other case statement in SystemVerilog?

Question

I have a SystemVerilog testbench in which I want to use a case statement in other case statements from my program.

For example, I have:

    task a(string b,string c)
    case(b)
     "a1": x(x1,case(c) "b1":y=1; "b2":y=2;);
     "a2": x(x2,case(c) "b3":y=4; "b4":y=5;);

This is the structure I want to implement, to use the case with string c in multiple different case items.

Answer 1

If I guess correctly, x represents a task or a function and you are trying to pass a case statement as an argument. right? impossible.

But this should work:

 task a(string b,string c)
    case(c)
      "b1": y = 1;
      "b2": y = 2;
      ...
    endcase

    case(b)
     "a1": x(x1,y);
     "a2": x(x2,y);

or for case within a case in general use begin/end:

     "a1": begin
            x=x1;
            case(c) 
              "b1":y=1; 
              "b2":y=2;
            endcase
           end
     "a2": begin
            x = x2;
            case(c)
              "b3": y=3;
              "b4": y= 4;
            endcase
           end
      endcase