Considering only dcache and dTLB. Due to the current L1d-cache being VIPT, it is necessary to obtain a physical address before cache hit.
Now, it is sure that the hit judgment of L1d-cache depends on the results of L1 dTLB. ref
But what if L1-dTLB misses, do CPU have to wait for the results of L2-TLB to return in order to access the data in L1d-cache?
What if L2-TLB also misses and a page walk is required? Is it unreasonable for the cache access operation to wait for page walks that require memory access?