Is micro kernel possible without MMU?

Question

In the following link; https://www.openhub.net/p/f9-kernel F9 Microkernel runs on Cortex M, but Cortex M series doesn't have MMU. My knowledge on MMU and Virtual Memory are limited hence the following quesitons.

1. How the visibility of entire physical memory is prevented for each process without MMU?
2. Is it possible to achieve isolation with some static memory settings without MMU. (with enough on chip RAM to run my application and kernel then, just different hard coded memory regions for my limited processes). But still I don't will this prevent the access?

Answer 1

Yes, but ....

There is no requirement for an MMU at all, things just get less convenient and flexible. Practically, anything that provides some form of isolation (e.g. MPU) might be good enough to make a system work - assuming you do need isolation at all. If you don't need it for some reason and just want the kernel to do scheduling, then a kernel can do this without an MMU or MPU also.

Answer 2

ARM Cortex-M processors lack of MMU, and there is optional memory protection unit (MPU) in some implementations such as STMicroelectronics' STM32F series.

Unlike other L4 kernels, F9 microkernel is designed for MPU-only environments, optimized for Cortex M3/M4, where ARMv7 Protected Memory System Architecture (PMSAv7) model is supported. The system address space of a PMSAv7 compliant system is protected by a MPU. Also, the available RAM is typically small (about 256 Kbytes), but a larger Physical address space (up to 32-bit) can be used with the aid of bit-banding.

MPU-protected memory is divided up into a set of regions, with the number of regions supported IMPLEMENTATION DEFINED. For example, STM32F429, provides 8 separate memory regions. In PMSAv7, the minimum protect region size is 32 bytes, and maximum is up to 4 GB. MPU provides full access over:

• Protection region
• Overlapping protection region
• Access permissions
• Exporting memory attributes to the system

MPU mismatches and permission violations invoke the programmable priority MemManage fault handler.

Memory management in F9 microkernel, can split into three conceptions:

1. memory pool, which represents the area of PAS with specific attributes (hardcoded in mem map table).
2. address space - sorted list of fpages bound to particular thread(s).
3. flexible page - unlike traditional pages in L4, fpage represent in MPU region instead.