Issue implementing a 4x1 multiplexer in verilog

Question

I had an issue with a 4x1 multiplexer. The code is below:

module mux4x1( select, d0, d1, d2, d3, q );

    input[1:0] select; //CWP 0, CWP 1

    input[31:0] d0, d1, d2, d3;

    output[31:0] q;
    wire[31:0] q;
    wire[1:0] select;
    wire[3:0] d;

    case (select)
      2'b00 : assign q = d0;
      2'b01 : assign q = d1;
      2'b10 : assign q = d2;
      2'b11 : assign q = d3;
    endcase 

endmodule

Unfortunately it gives me the following errors when i try to use it elsewhere:

testbench.sv:613: error: Unable to bind parameter select in `testModule.RWTest.mux1' testbench.sv:613: error: Cannot evaluate genvar case expression: select

Line 613 is the case (select) line. I've looked into this quite a bit, and i've seen extremely similar code in other situations, so i'm not sure what the issue is exactly.

Answer 1

You need to put the case statement inside a procedural block like so:

always @(*) begin
  case (select)
    2'b00: q = d0;
    2'b01: q = d1;
    2'b10: q = d2;
    2'b11: q = d3;
  endcase
end

Remember, all logic needs to either be inside a combinational block using always @(*) like the above code or in a separate assign statement. Note that these should be "top level" within the module, ie no logic surrounding the assign like you have attempted to do in your code.

Note that as a result of this change, you will need to modify the type of q to be reg instead of a wire (also remember that reg type does not be a literal hardware register, its one of the more confusing things about learning Verilog unfortunately)