iverilog errors likely stemming from incorrect variable types

Question

I am new to verilog programming and am working on implementing an 8-bit unsigned magnitude comparator using 2 4 bit comparators. I believe my code is implemented correctly, however I am recieving errors which I believe are due to incorrect variable type assignments. As I am new to the language, I consider this a learning opportunity, however I cannot find enough relevant material to lead me to a solution. If someone could explain why the types I am using are incorrect (or if it is a different problem I am facing) it would be much appreciated.

EDIT: I changed my answer to that suggested, with module instantiation outside of the always block and wires as eq, gt, and lt, but am still getting errors. Updated the error code.

module MagComp4Bit (input [3:0] a, input [3:0] b, output eq, output gt, output lt);

    assign eq = a==b;
    assign gt = a>b;
    assign lt = a<b;

endmodule

module MagComp8Bit (input [7:0] a, input [7:0] b, output eq, output gt, output lt);

    reg eq0, gt0, lt0, eq1, gt1, lt1;

    MagComp4Bit comp1(a[3:0], b[3:0], eq0, gt0, lt0);
    MagComp4Bit comp2(a[7:4], b[7:4], eq1, gt1, lt1);
    always @(a, b)
    begin


            if (eq1) begin
                    eq = eq0? 1 : 0;
                    gt = gt0? 1 : 0;
                    lt = lt0? 1 : 0;
            end
            else begin
                    gt = gt1? 1 : 0;
                    lt = lt1? 1 : 0;
            end
    end
endmodule

module TestComparator;
    reg[7:0] a, b;
    wire eq, gt, lt;

    MagComp8Bit compare(a, b, eq, gt, lt);

    initial begin
            $moniter("%d a=%b, b=%b, eq=%b, gt=%b, lt=%b",
                    $time, a, b, eq, gt, lt);

            #10     a = 2;
                    b = 5;
    end
endmodule

error message:

hw1p1.v:13: error: reg eq0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 3 (eq) of MagComp4Bit is connected to eq0
hw1p1.v:13: error: reg gt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 4 (gt) of MagComp4Bit is connected to gt0
hw1p1.v:13: error: reg lt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 5 (lt) of MagComp4Bit is connected to lt0
hw1p1.v:14: error: reg eq1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 3 (eq) of MagComp4Bit is connected to eq1
hw1p1.v:14: error: reg gt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 4 (gt) of MagComp4Bit is connected to gt1
hw1p1.v:14: error: reg lt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 5 (lt) of MagComp4Bit is connected to lt1
hw1p1.v:22: error: eq is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : eq is declared here as wire.
hw1p1.v:23: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:24: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
hw1p1.v:27: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:28: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
17 error(s) during elaboration.

(P.S. I am aware it is improper to include a test bench with other modules, but it is easier for me to learn when I can see it all at once.)

Answer 1

Verilog modules are not intended to be instantiated inside of initial or always blocks. That is why you should move:

MagComp4Bit(a[3:0], b[3:0], eq0, gt0, lt0);
MagComp4Bit(a[7:4], b[7:4], eq1, gt1, lt1);

outside always block. What is more, eq, gt, lt should be declared as wires in your TestComparator module.

Answer 2

wire type cannot be assigned in any procedural block (always, intial, ..). You are doing jus that inside of the always

always...  
    .. 
    eq = eq0? 1 : 0;

where eq is defined as a port without any data type, which means wire by default. same about other 2 ports: lt and gt.

You need to change your code a bit:

reg eqReg, ltReg, wrReg;

always @(a, b)
    begin

        if (eq1) begin
                eqReg = eq0? 1 : 0;
                gtReg = gt0? 1 : 0;
                ltReg = lt0? 1 : 0;
        end
        else begin
                gtReg = gt1? 1 : 0;
                ltReg = lt1? 1 : 0;
        end
end
assign eq = eqReg;
assign lt = ltReg;
assign gt = gtReg;