Linux Kbuild: what is the difference between $(src) and $(obj)

Question

In Documentation/kbuild/makefiles.txt chapter 3.10 it is mentioned that $(src) refers to the location of the source code while $(obj) refers to the location of the generated output files. I am confused about this when using a different output directory.

In Makefile.build the very first thing that is done is src := $(obj). How does that make any sense? If I print $(src) and $(obj) they always have the same value.

However, what is even more confusing to me, is that if this was the case, make should issue an error. If the working directory is outside the kernel source (O=path/to/out/dir) when the rule $(obj)/%.o: $(src)/%.c is evaluated it should search for the source file relative to the output directory. And since the source file is not there it should fail saying it cannot find a rule for $(src)/%.c target.

Can someone please explain what I'm getting wrong here?

Answer 1

Answering my own question in case others wondered about this...

The main Makefile uses vpath to add the src location, so when kbuild does not find the source file in the output tree it will find it in the source tree.