List of Hidden ARM 3 Letter mnemonics

Question

x86 has had cases of the manufacturer inserting, new, undocumented opcodes at the time¹.

Due to ARM holdings lack of a fab plant, there could be 'hidden' opcodes inserted by the licentiate. After using my google-fu this theory seems to be incorrect. From documentation, or past experiences -- do you know of any 'hidden mnemonics'?

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Footnote 1: For example x86's 0xD6 opcode which some assemblers support as salc (Set AL from Carry, like sbb al,al which sets it to 0 or -1 but without updating FLAGS). https://righto.com/2023/07/undocumented-8086-instructions.html - it exists in Intel CPUs from 8086 to present in modes other than 64-bit, and in most (all?) CPUs from other vendors, too. It's still not documented in Intel manuals, but is mentioned by AMD's manual in a table of instructions not available in 64-bit mode, despite it not being documented in the rest of the manual.

https://pushbx.org/ecm/doc/insref.htm is a corrected version of NASM's appendix from when it had descriptions; you can search on [UNDOC] in it for some other 286, 386, and 486 undocumented instructions.

Other x86 vendors have had their own undocumented opcodes, like Via C3 CPUs have an "alternate instruction set" activated by a special opcode. (See Why does Intel hide internal RISC core in their processors?, and Christopher Domas's "Breaking the x86 Instruction Set" talks about finding these and other undocumented opcodes.)

Answer 1

XScale can be a very visible example of such fork. Intel at the time added own instructions to provide a more media capable core.

From Intel XScale® Core Developer’s Manual:

2.3 Extensions to ARM Architecture

3rd generation microarchitecture extends the ARMv5TE architecture to meet the needs of various markets and design requirements. The following is a list of the extensions which are discussed in subsequent sections.

• A Media Processing Co-processor (CP0) has been added that contains a 40-bit internal accumulator. Five new instructions have been added which access the 40- bit accumulator. Page Attributes were added to the page table descriptors and the description of existing attributes in ARMv5TE were enhanced. Note that compatibility is maintained with software developed using page table attributes for previous microarchitectures.
• Co-processor 7 and Co-processor 14 registers are added to 3rd generation microarchitecture.
• Co-processor 15 functionality is extended and new registers are added.
• Enhancements were made to the Exception Architecture, which include instruction cache and data cache parity error exceptions, debug exceptions, and imprecise external data aborts.

Qualcomm at the writing time of this post is like Intel but with a more closed approach. May be they don't directly add new instructions to their cores but they try to modify them in a way to give them advantage over other ARM cores. An example to this is SIMD instructions, Qualcomm has its own co-processor called VeNum and that has some less limitations of register addressing as compared to ARM cores - read Michael's comment as an example.