LLVM: Disable some instructions while generating machine code

Question

I do not want to use particular machine instruction in my generated assembly code by llvm.

Is there way to disable the same? I'm ok with modifying the llvm code also.

Answer 1

One solution is to specify to llvm that this instruction cannot be "lowered"... Two things may happen:

• the compiler can perform the same operation with another combination of instructions... things will be okay
• the compiler cannot do without it, in which case you have to modify the target generator to suggest a workaround (not quite easy if you're not familiar with llvm)

To do that search for XXXISelDAGToDAG.cpp, where XXX is your target machine and specify to the constructor something like:

setOperationAction(ISD::YYY, MVT::i8, Expand);
setOperationAction(ISD::YYY, MVT::i16, Expand);
setOperationAction(ISD::YYY, MVT::i32, Expand);
setOperationAction(ISD::YYY, MVT::i64, Expand);

Where ISD::YYY is the instruction you don't want to use. This is quite easy to locate when browsing the source code.

Roughly:

• setOperationAction specifies that you want to change the default action for a given operation, along with the type (MVT::...)
• Expand means "try to expand to another operation" (there are other actions, such as Custom, Libcall...)

Playing around with that, you should be able to solve your problem.

Hoping it will help.