Matching different/multiple parts of a Makefile target

Question

Here is a Makefile that I currently use to make targets with different configurations, i.e., I am building different software packages with the same target, either all at once or individually.

.PHONY: build test %.build %.test build-all test-all
%.build %.test: PACKAGE = $*

%.build:
    @echo build $(PACKAGE)

%.test:
    @echo test $(PACKAGE)

build-all: a.build b.build
test-all:  a.test  b.test

build: $(PACKAGE).build
test:  $(PACKAGE).test

I can now build all packages with make build-all or individual packages with, e.g., make build PACKAGE=a. However I would like to switch the body of the %.build and build, etc. targets as in the following:

.PHONY: build test %.build %.test build-all test-all
build:
    @echo build $(PACKAGE)

test:
    @echo test $(PACKAGE)

build-all: a.build b.build
test-all:  a.test  b.test

%.build %.test: PACKAGE = $*
$(PACKAGE).%: $*

This way, the pattern matching logic is fully separated from the "main" targets build and test that should contain the actual build commands; making the important parts of the Makefile more readable. However, the last line does not work as intended, i.e., running make a.build and thus make build-all should trigger the target build with PACKAGE=a. The variable assignment in second-last line works, the target matching in the last line does not.

Question: Is there a way to express a matching target like $(PACKAGE).%: $* or to match separate parts of a target like %.%: $2?

Answer 1

First you probably want:

$(PACKAGE).% : %

not using $*, which is an automatic variable and so it has no value except inside the recipe; you can't use it like that in the prerequisite lists.

Second, you can't do this in GNU make. A pattern rule with no recipe doesn't just a create prerequisite relationship, like an explicit rule would do; instead it deletes the pattern rule. Since you didn't have a pattern rule for $(PACKAGE).% yet, this is basically a no-op. Also, target-specific variables are only available inside the recipe, so trying to use $(PACKAGE) in the target definition and expecting it to take the value from some previously set target-specific variable cannot work.

You could do something like this, but it's not fully dynamic (you still need the list of packages and types):

PACKAGES = a b
TYPES = build test

$(foreach T,$(TYPES),$(eval $(addsuffix .$T,$(PACKAGES)): $T))

Answer 2

As MadScientist explained, the problem cannot be solved easily in GNU make. For completeness, I would like to add and explain my final and more comprehensive solution:

.PHONY: all build test clean %.build %.test build-all test-all

PACKAGES  = a b c e f g
PACKAGE   = a

all: clean build-all test-all

%.build %.test: PACKAGE = $*

%.build:
    @echo build $(PACKAGE)

%.test:
    @echo test $(PACKAGE)

clean:
    @echo remove build dir

build-all: $(addsuffix .build, $(PACKAGES))
test-all:  $(addsuffix .test,  $(PACKAGES))

build: $(PACKAGE).build
test:  $(PACKAGE).test

This solution avoids eval and foreach and is based on my initial working solution, where the dynamic %.build and %.test targets contain the actual build commands. I added the PACKAGES variable to facilitate easy addition of new packages, a default PACKAGE to prevent execution of misconfigured build commands, and the common targets all and clean as complements.

From the command line, you just call make all, clean, build PACKAGE=x, build-all, etc., i.e., only the static targets, which will then trigger the build commands in the dynamic targets. The static targets and the two variables are also visible in the Bash/Zsh auto-completion.

I think this is the most flexible and yet readable way to build multiple dynamic targets.