I'm working on a uboot test application that will work with a special DMA engine. The DMA engine will transfer data between memories without "notify" cache. Therefore, I expect that if I keep transferring different data to the same destination, I should get the stale data.
However, I found that I always get the correct data the DMA engine sent. This makes me think that maybe the dcache is not enabled. So I tried the uboot build-in cmd - dcache. It shows my data cache is enabled. And I checked the TLB table and all pages are marked as "write back write allocate". So it means the cache is enabled?
And more interesting thing I found is that, I wrote a simple program that just keeps reading the same address. And I found that by disabling the dcache using the dcache cmd, the time to run the test just tripled. I tried a similar simple test in Linux on the same hardware and the cache can enable more than 15 times performance boost. So this must not be a hardware issue.
In summary, I found that my cache is working to some extent but not fully working. And it might be a configuration issue. Is there any theory can explain what I found? How can I continue to debug... Thanks
Let me answer it myself...
Code in Uboot is a little misleading... it run
set_section_dcache(i, DCACHE_WRITEBACK_WRITETHROUGH)
but after checking the MMU, it turns out that the memory type is set to be device.