MIPS Pipeline forwarding: How to forward to the second succeeding instruction?

Question

Say, for example, I have 3 instructions: 1, 2, and 3.

I want to forward data from instruction 1 to instruction 3. The catch is, I can only forward from the EX/MEM register of instruction 1.

So we have:

1:    IF ID EX MEM WB
2:       IF ID EX  MEM WB
3:          IF ID  EX  MEM WB

and I want to forward from EX/MEM of 1 to ID/EX of 3.

This is part of a homework problem, and apparently I need to stall an instruction. I don't see how this would help anything in the slightest, since it already makes no sense for me to forward data forward in time.

Problem in question:

Answer:

Thanks for any help

Answer 1

... since it already makes no sense for me to forward data forward in time.

Data can only be forwarded forwards in time, not backwards, since as of 2021, we still don't have time machines.

So, forwarding necessarily feeds information available in the processor generated just right now, to somewhere else in the processor, so it can be used in the future (i.e. the next cycle).

Forwarding and stalling are both ways to mitigate a RAW hazard — the idea is simply to get a value from where generated to where needed.

If the "where needed" is earlier in time than the "where generated", then a stall is required.  However, if the "where needed" is later in time than the "where generated" then a forward can mitigate the hazard.  The hazard is caused by the pipeline's assumption that "where needed" is the register file, which is incorrect in back to back operations.

Some hazards require both a forward and a stall, as the best that can be done.

But all hazards can be mitigated with sufficient stalling and without forwarding, though that will reduce performance.  With sufficient stalling, the "where needed" and the "where generated" can both be the register file.

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The catch is, I can only forward from the EX/MEM register of instruction 1.  and I want to forward from EX/MEM of 1 to ID/EX of 3.

We cannot forward from EX/MEM of 1 directly to ID/EX of 3.  Why?  Because, ID/EX of 3 is two cycles further along, so the data we want to forward from there (EX/MEM of 1) is no longer there: it has moved down the pipeline to the next stage.  By the time that ID/EX of 3 wants that data, that data is now in MEM/WB (e.g. of 1) — EX/MEM at that time is doing instruction 2.