I have some questions on MMIX's interrupt. The definition of the special register rK is "interrupt mask register". But it seems it treat different event differently.
for I/O bits(let's call ** bit: This is a normal case. When an external interrupt come, if rK's ** bit is 0, rQ's ** bit will hold '1' until rK's ** bit is set to 1, and the trap will occur.
for S-bit (program): Accroding to the source-code of
mmix-pipe, even when rK's S-bit is 0, a security exception will occur. and rK's S-bit will be alter from 0 to 1. So, in positive-address, rK's S-bit should be 1, and in negative-address rK's S-bit don't have any effect. Only rQ's S-bit is used to tell system that "there was a security issue", rK's S-bit seems useless.for P-bit (program): It is sad "instruction comes from a privileged (negative) virtual address." in mmix-doc.pdf. But if PC is in a negative-address, rQ's P-bit will not always be set to 1. (mmix-pipe also not set rQ's P-bit).
I can prove it: If all the instructions that executed before the "resume" insn will set rQ's P-bit to 1, then resume will also set rQ's P-bit to 1. As a result, after the resume, the 'user' insn will always trigger a TRAP. that is impossible. So when P-exception is inhibited, rQ's P-bit will not set to 1.
so rK's P-bit is not just used as a mask, it is used as a "option to bypass a exception-checking".
Here are some questions.
Why not make all rK's bits just as a mask for interrupt? Is there any reason made S/P bits so strange?
do other rQ's program bits (rwxnkb) set to 1 if rK's corresponding bits is 0?
As in Neg-address, trip will not occur, do DVWIOUZX bits hold 1 after it just happened?