Modelica DFFR used in a phase-frequency detector

Question

Gretings:

I hope my email finds you well.

I am working on a openModelica phase locked loop (PLL) project. It consist of a phase frequency detector (PFD), a loop filter (LF) and a voltage controlled oscillator (VCO) The PFD circuit I am modeling is below:

enter image description here

I am driving the A and B inputs from the digitalclocks in the openModelica library. I am also using two DFFRs and an And gate from the library. The clock signals at inputs A and B are staggered in phase. The DFFRs are suppose to reset when the Resets are at a logic level 1. The outputs should look like the bottom two traces. However, the outputs are stuck at logic level 1.

I determined that the digitalclocks switch between 3 and 4V. Also, the transition voltage for the DFFRs is suppose to be 2.5V. So the DFFRs never see a logic 0 at eh clock inputs. So, the circuit above does not function.

I also found, the digitalclocks with NOT let me adjust the level of the output voltage. So currently, the clocks cannot drive this PFD.

If anyone has experience working with flip flops in the Modelica library, I would appreciate your help.

Note:

1. My current OS is Windows 11

2. I am using the latest version of opeModelica 1.21.0

penModelica. It was very frustrating trying to figure out why this circuit was operating correctly.

Thank you in advance for your help with this matter.

Cheers!

Frank

I have looked at the specs of the components used in this model.

I spoke with some of the architects of Modelica/openModelica. However, they did not design the digital library.

I have modeled this circuit in QSpice and the model works fine.