ModelSim Register is illegal error

Question

So i am getting the error

** Error: C:/Modeltech_pe_edu_10.3c/examples/HW6/alu.v(53): Register is illegal in left-hand side of continuous assignment

for the assign statement [assign result = 32'd0;] any ideas why? i have tried moving that cluster of statements all around the code and the only way it works is if i completely remove the part of the code.

Issue there is that i need that to run my test bench. Any ideas on what this error means and how to solve it?

//
    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

    module alu
    (
        //--------------------------
        // Input Ports
        //--------------------------
            input   [31:0]  operand0, 
        input   [31:0]  operand1, 
        input   [3:0]   control,
        //--------------------------
        // Output Ports
        //--------------------------
            output reg  [31:0]  result,
        output          zero,
        output      overflow



    );
        //--------------------------
        // Bidirectional Ports
        //--------------------------
        // < Enter Bidirectional Ports in Alphabetical Order >
        // None

        ///////////////////////////////////////////////////////////////////
        // Begin Design
        ///////////////////////////////////////////////////////////////////


            assign  result  = 32'd0;
        assign zero     = 1'b1;
        assign overflow = 1'b0;




    always @(*)


    begin
    case(control)




    4'b0000: result = operand0 && operand1;

    4'b0001: result = operand0 || operand1;

    4'b0010: result = operand0 ^ operand1;

    4'b0011: result = !(operand0 || operand1);

    4'b0100: result = operand0 + operand1;

    4'b0110: result = operand0 - operand1;

    4'b1000: result = operand0 < operand1;

    4'b1001: result = operand0 << operand1;

    4'b1010: result = operand0 >> operand1;

    4'b1011: result = operand0 >>> operand1;
    endcase

    end



    endmodule

Answer 1

First: a type reg cannot be assigned in an assign statement; it is a rule of Verilog. "Register is illegal in left-hand side of continuous assignment" mean a register can not be assigned by a assign statement. left-hand side as in left of the =.

Second: Even if a type reg could be assigned in an assign statement, you will have multiple drivers on result as it is being assigned in the always block. assign statements are continuous drivers, meaning it will always be applying a value to the signal no matter other blocks are doing to the same signal. If there are any conflicts (ex one applies 1 and the other applies 0) the result will be 'bx;

Solution: Remove the line: assign result = 32'd0; result is combinational logic and does not need an initial value.