On bare-metal, non-OS, how context switching occurs upon exceptions/interrupts

Question

When CPU receives exception, Pre-processing by hardware Saving the current PC and PSW values in RAM (or in control registers in the case of the fast interrupt) and Reading of the vector Branching to the start of the exception handling routine is done.But, General purpose registers and control registers other than the PC and PSW that are to be used within the exception handling routine must be preserved on the stack by user program code at the start of the exception handling routine. Reverse is repeated by user code and hardware upon returning from exception. (Reference: Renesas Rx62n hardware manual, page 297, Chapter:Exceptions)

My question is where is this user code for context switching and how it is getting called?

Answer 1

As per the Renesas CC-RX compiler document, To declare any global function as ISR we need to specify it as

#pragma interrupt func
void func (void) { ... }

and compiler will generate code for it as:
func:
PUSHM R1-R3; Saves the registers used in the function.
....
(R1, R2, and R3 are used in the function)
....
POPM R1-R3; Restores the registers saved at the entry.
RTE

Additionally, we can also specify some other parameters such as:
fast interrupt (in this case PC and PSW will be saved in Backup BPC and BPSW by hardware, otherwise on stack)
acc save/restore
nesting enable
use limited registers in interrupt functions and don't generate instruction for saving/restoring R6-R13 registers.

This solves my doubt.