Optional Randomization of enum variable

Question

I am writing a Testbench using Systemverilog and I want to have the freedom to choose in each test to either randomize some variables or specify their value (from a .do file or from command line). Is there any option in Systemverilog to do this?

Answer 1

There are many things you can do, but the simplest is putting +some_variable=value on the command line, and then in your code

if (!$value$plusargs("some_variable=%0d",some_variable)
   some_variable = $urandom;

Answer 2

Declare a variable and use $urandom or $urandom_range to generate random values. When you want to pass values from the command line, you can use $value$plusargs.

Read up on Chapter 21 (Input/output system tasks) of the LRM to find examples.