I have a custom board with freescale P1010 processor in which P1010's eTSEC2 ( Enhanced 3-speed Ethernet controller) port is directly connected to Marvell 88E6046 ethernet switch Port 9 in SGMII mode. Linux (3.17) DSA driver is able to probe and detect switch ( Port 9 is 'cpu' whereas port 0 and 1 are designated as 'lan1' and 'lan2'). The problem however is, that there is no PHY for switch to attach to ( 'ifconfig up' fails to attach to ethx). U-boot creates a 'generic PHY' eth0 since it finds there is something ( switch ) attached to processor P1010 but when Linux is up and switch is attached to this 'generic PHY' (eth0) I am not able to ping it ( lan1 or lan2 though DSA link is up). There are 2 reasons for this behaviour that I can think.
- Switch port 9 is directly connected to processor MAC in SGMII mode but without any external PHY in between.
- Even when switch is directly connected, it is not configured in 'Reverse MII' mode, hence internel PHY at Port 9 is not detected.
Given the above scenario is it still possible for ethernet switch to work using DSA driver ?
Also I tried using Processor's internal PHY to attach it to eth0 but couldn't. Somehow gianfar ethernet driver always finding external PHY while there is none. It never looks for internal PHY even when 'fixed-link' property is defined in dts file. Also in my design MDC and MDIO lines of processor are connected to Switch. In processor to switch PHYless MAC-MAC connections, does it creates 2 Masters ? Should these be disconnected ? Is it because of MDC/MDIO connections I'm not able to access internal PHY of P1010 processor?