python myhdl package how to generate verilog initial block

Question

From the code mostly from the sample of myhdl:

from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog

__debug = True

def ClkDriver(clk):
    halfPeriod = delay(10)
    @always(halfPeriod)
    def driveClk():
        clk.next = not clk
    return driveClk

def HelloWorld(clk, outs):

    counts = intbv(3)[32:]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts >= 3 - 1:
            counts.next = 0
        else:
            counts.next = counts + 1
        if __debug__:
            print "%s Hello World! outs %s %s" % (
              now(), str(outs), str(outs.next))

    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)

I expect it to generate a verilog program that contains an initial block, like something:

module HelloWorld(...)
reg [31:0] counts;
initial begin
    counts = 32'h3
end
always @(...

How can you get the initial block generated?

Note that on the google cache for old.myhdl.org/doku.php/dev:initial_values it links to example https://bitbucket.org/cfelton/examples/src/tip/ramrom/ . So it looks the feature should be supported. However the rom sample generates static case statements. That's not what I'm looking for.

Answer 1

Three steps to resolve it:

• Update to the latest myhdl on master or a version that contains the hash 87784ad which added the feature under issue #105 or #150. As an example for virtualenv, run a git clone, followed by pip install -e <path-to-myhdl-dir>.
• Change the signal to a list.
• Set toVerilog.initial_values=True before calling toVerilog.

Code snippet follows.

def HelloWorld(clk, outs):

    counts = [Signal(intbv(3)[32:])]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts[0] >= 3 - 1:
            counts[0].next = 0
        else:
            counts[0].next = counts[0] + 1
        if __debug__:
            print "%s Hello World! outs %s %s %d" % (
                  now(), str(outs), str(outs.next), counts[0])
    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
toVerilog.initial_values=True
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)