Snooping memory access in x86 cpus

Question

I'm reading about cache control protocol as it is documented in Intel Manual Vol.3(p11). The thing that is unclear is snooping memory access. Here is its description:

Beginning with the P6 family processors, if a processor detects (through snooping) that another processor is trying to access a memory location that it has modified in its cache, but has not yet written back to system memory, the snooping processor will signal the other processor (by means of the HITM# signal) that the cache line is held in modified state and will preform an implicit write-back of the modified data. The implicit write-back is transferred directly to the initial requesting processor and snooped by the memory controller to assure that system memory has been updated. Here, the processor with the valid data may pass the data to the other processors without actually writing it to system memory; however, it is the responsibility of the memory controller to snoop this operation and update memory.

Consider the following cache state (according to MESI):

       CPU1    CPU2   CPU3
Line1   M       I      -

CPU2 writes to Line1.

This is how I see snooping:

1. CPU2 performs write to a memory that is cached in Line1.
2. CPU1 snoops around and finds the write performed by CPU2.
3. CPU1 signals other CPUs with HITM# that the Line1 is in modified state

4. CPU1 performs write-back of Line1 data OR since CPU1 has valid data at the moment the data will be transffered to both CPU2 and CPU3 transferring the Line1 into Shared (S) state.

5. CPU2 performs the actual write transferring the Line1 in its cache in the Modified (M) state and Line1 in CPU1 and CPU3 in the Invalid (I) state.

So by snooping memory access system bus access can be avoided maintaining cache coherency even in case if some CPU writes into a memory location that is in an cached in Invalid line. Is that basically what they meant by snooping?