STM32 - What is sampling frequency of ADC

Question

I use ADC3 on STM32H7, I need to know (and set) what is sampling frequency. I use 3 channels in 16 bits. What I tried to calculate?

1. From this image I should have Fadc_ker_ck = 30 MHz, becase my CKMODE = 0b11, and adc_sclk = 480/2 = 240 MHz (HPRE=2) - so it is sys_clk/2
2. Tconv_time = 8.5(setable)+8.5(fixed for 16 bits) = 17 ADC clock cycles = 17/30Mhz = 566 ns

Form above the Tconv should be 17/30Mhz = 566 ns

What about sampling frequency? My PRESC in ADC3_CCR = 0b1010 (divide by 128) So I should divide some_CLK/128. What is the some_CLK? Is it the Fadc_ker_ck = 30 MHz?? Then it would be 30Mhz/128 = 234,375 kHz = 4,266 usec

Experiments:

I use BDMA for continual ADC3 measurement, I converts 200 samples for each chanels (3) = 600 samples.

I can measure the conversion time for all 3 channels - it takes 34.82 ms.

=> It is 600samples/34.82 ms => 1sample/58usec

So: measured time for 1 sample is 58 usec = 17,241 kHz calculated time for 1 sample is 4.266 usec = 234,375 kHz

What I did wrong?

Also I am not sure if Tconv is dependent on PRESC in ADC3_CCR. From datashet I think it is not dependant:

Thank you very much

Answer 1

So now it is solved.

everything above about Tconv (sampling time) is corect. And because the clock I used is adc_sclk, so no DIV in ADCx_CCR register has effect on sampling frequency - that was probably main mistake I did.

Then if 1 sample takes 566 ns, then when I measure on all 3 channels, so measure period of first channel is 566*3 ns. And no another div has effect on this period...