Is there meant to be any functional difference between making a wire "tri0" vs applying a "pulldown" component to the wire?
systemverilog : tri0 vs pulldown - is there any difference?
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In most cases, declaring a signal to be
tri0is functionally equivalent to declaring that signal as awireand connecting the signal to apulldown.There is an exception when you pass that signal through a port, and make a connection to a signal with a dissimilar net type (See section 23.3.3.7 Port connections with dissimilar net types (net and port collapsing) in the IEEE 1800-2017 LRM). For that reason, I recommend that you use the pulldown to avoid confusion.