timescale definition in modelsim

Question

I have an issue while simulating my system with a verilog bench. I have a signal (clk_out) from which I want to measure and auto-check the period and both high and low time. Signal clk_out has a period of 1 second and both high time and low time are 500ms.

`timescale 1ms / 1ps 

module tb;

parameter PASSED = 1;
parameter FAILED = 0;

wire clk_out;
reg reset_n;
reg result;
realtime time1;
realtime time2;
realtime time3;


initial begin
result            = PASSED;
reset_n           = 1'b0;

// stay in reset for 100ms
reset_n = #100 1'b1;

@(negedge clk_out);
time1 = $realtime;
@(posedge clk_out);
time2 = $realtime;
@(negedge clk_out);
time3 = $realtime;

$display("\n");
$display("period is %f, high time is %f, and low time is %f",time3-time1,time3-time2,time2-time1);
$display("\n");

if (time3-time1 <= 999 || time3-time1 >= 1001) begin
  result = FAILED;
end

if (time2-time1 <= time3*0.998/2 || time2-time1 >= time3*1.002/2) begin
  result = FAILED;
end

if (time3-time2 <= time3*0.998/2 || time3-time2 >= time3*1.002/2) begin
  result = FAILED;
end

$display("\n");
$display("=================================================");
if (result) begin
$display("Test is PASSED");
end else begin
$display("Test is FAILED");
end

// create the 1Hz signal when not in reset
my_module my_module_under_test
(
  .RESET_N (reset_n),
  .CLK_OUT (clk_out)
);

modelsim output is as follow :

period is 1000000000.000000, high time is 500000000.000000, and low time is 500000000.000000

=================================================

test is FAILED

=============== END OF SIMULATION ===============

It seems that the timescale define at the file top is not read by the simulator. I expected to have :

time3 - time1 = 1000.00000

time2 - time1 = 500.00000

time3 - time2 = 500.00000

What am I doing wrong ?

Thanks

Answer 1

I have converted your code to a self contained test, no my_module, on EDA Playground.

It outputs as you expected.

# time3-time1 : 1000.000000
# time3-time2 : 500.000000
# time2-time1 : 500.000000

If your still having the issue I would suggest there is an issue is in the my_module that the clock is not running at the correct frequency.

Tips:
1) I would change the way your applying your reset from:

// stay in reset for 100ms
reset_n = #100 1'b1;

to

// stay in reset for 100ms
#100ms reset_n =  1'b1;

The last version will sequentially wait for 100ms then release the reset, before moving on to the rest of the test program.

2) If your simulator supports it using time specifiers helps remove reliance on the timescale. ps pico seconds, ns nanoseconds, ms milliseconds, s seconds.

Answer 2

Two possibilities:

1. Check the timescale declared above module my_module(...), the module will use this time scale. If the time scale is not declared in the file, then it will used the most recently declared timescale; compiling order matters. If no previously compiled timescale is declared, then it will use the simulators default timescale.

2. if the command line option -timescale timeunit/timeprecision it is used, it will the global timescale and any declaration in the verilog files will be ignored.