TLB Cache Invalidation when EPT Violation occurs?

Question

I'm currently developing a hypervisor feature.
I'm confused about what to do with TLB Invalidation when EPT Violation occurs

I'm developing on Linux, using an i7 CPU. My implementation:

• VPID and EPT Enabled
• Initially, every EPT entries' write access is cleared (read and execution access is set)
• If EPT Violation occurs(when tries to write), set write access and change entry to point another page(another hpa)

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According to Intel Manual,

"An EPT Violation invalidates any guest-physical mappings (associated with the current EP4TA) that would be used to translate the guest-physical address that caused the EPT Violation. And also invalidates any combined mappings too"

I'm confused with this part.

Does it ensures that EPT Violation invalidates corresponding TLB Entry not only in the current core's TLB cache but also other core's TLB Cache?

If so, is it OK just setting write access and allocating new hpa without tlb shootdown?

Answer 1

I think you need to worry about clearing other core's TLB cache.

If you read above the part of Intel manual you quoted, you will find that the paragraph applys to a single logical core:

27.3.3 Invalidating Cached Translation Information

Software modifications of paging structures (including EPT paging structures and the data structures used to locate SPP vectors) may result in inconsistencies between those structures and the mappings cached by a logical processor. Certain operations invalidate information cached by a logical processor and can be used to eliminate such inconsistencies.

27.3.3.1 Operations that Invalidate Cached Mappings

The following operations invalidate cached mappings as indicated:

Operations that architecturally invalidate entries in the TLBs or paging-structure caches independent of VMX operation (e.g., the INVLPG and INVPCID instructions) invalidate linear mappings and combined mappings.1 They are required to do so only for the current VPID (but, for combined mappings, all EP4TAs). Linear mappings for the current VPID are invalidated even if EPT is in use.2 Combined mappings for the current VPID are invalidated even if EPT is not in use.3

An EPT violation invalidates any guest-physical mappings (associated with the current EP4TA) that would be used to translate the guest-physical address that caused the EPT violation. If that guest-physical address was the translation of a linear address, the EPT violation also invalidates any combined mappings for that linear address associated with the current PCID, the current VPID and the current EP4TA.

If the “enable VPID” VM-execution control is 0, VM entries and VM exits invalidate linear mappings and combined mappings associated with VPID 0000H (for all PCIDs). Combined mappings for VPID 0000H are invalidated for all EP4TAs.

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FYI the SDM I am using has Order Number 325384-075US, released in June 2021

Also, I feel that if EPT violation handles TLB shootdown for you, it will be very inefficient, or Intel should provide hardware support for traditional TLB shootdown (i.e. TLB shootdown that has nothing to do with virtual machines).