Tool-specific definition in (System)Verilog, especially by quartus and Synopsys DC

Question

I am writing a toy CPU with (System)Verilog. And there is a register module for which I am using tool-specific IP. DW_ram in DesignWare in terms of Synopsys Design Compiler. Altera_sync_ram in terms of FPGA by Altera.

Is there any definitions that Synopsys DC or Quartus Prime Pro would automatically pass to the parser to make one piece of code compatible for both tools?

Because if there is at least one such definition (say DESIGNCOMPILER for DC), the following code would be possible.

`ifdef DESIGNCOMPILER
     DW_RAM my_register (.*);
`else
     Altera_sync_ram my_register (.*);
`endif

Thanks in advance.

Answer 1

Synopsys Design Compiler supports the ifdef directive. Definitions can be passed to the tool while reading the design as in the example below.

analyze -format sverilog -define DESIGNCOMPILER MyDesign.sv