Verilog calculator with 16 bit inputs

Question

Hey guys I'm stuck on a project and am looking for some insight. The problem is: Build a Verilog module named “calculator” that takes in two signed 16-bit numbers named “in1” and “in2” and performs the following functions depending on the value of a third 4-bit input named “opCode” (see table below). The outputs of the module “calculator” must be a signed 16-bit number named “result”, and a 1-bit “overflow”. Be aware that the value of “overflow” doesn’t always get calculated the same way, it depends on the operation. The value of the output “overflow” will be one if an overflow occurred or the value of “result” is not completely accurate or correct; else the output “overflow” will be zero.DO NOT use $display or $monitor statement

I have done most of it but am having a hard time detecting overflow when opCode == 0010, 0011, 1000, and 1001.

Here is what I have so far:

module Calculator(in1,in2,opCode,result,overflow);

input signed[15:0] in1, in2;

input[3:0] opCode;  
output reg signed[15:0] result;
output reg overflow;

always @ (*) begin
if(opCode == 0000) begin
   if(in1+in2<=32767 & in1+in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end
always @ (*) begin
   if(opCode == 0001) begin
   if(in1-in2<=32767 & in1-in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end
always @ (*) begin
   if(opCode == 0010) begin
   if(in1*5<=32767 & in1*5>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end
always @ (*) begin
   if(opCode == 0011) begin
   if ((in1 % 10) == 0) begin
   overflow = 0;
end else begin
   overflow = 1;
end
   end
end
always @ (*) begin
   if(opCode == 0100) begin
   overflow = 0;
       end
end
always @ (*) begin
if(opCode == 0101) begin
   overflow = 0;
       end
end
always @ (*) begin
   if(opCode == 0110) begin
   overflow = 0;
       end
end
always @ (*) begin
   if(opCode == 0111) begin
   overflow = 0;
       end
end
always @ (*) begin
   if(opCode == 1000) begin
   if(in1 == 32767) begin
       overflow = 1;
       end
       else begin
       overflow = 0;
       end
       end
end
always @ (*) begin
   if(opCode == 1001) begin
   if(in1==-32768) begin
       overflow = 1;
       end
       else
       begin
       overflow = 0;
       end
       end
end
always @ (*) begin
case(opCode)
4'b0000: result = in1+in2; //add
4'b0001: result = in1-in2; //subtract
4'b0010: result = in1*5; //mult by 5
4'b0011: result = in1/10; //divide by 10
4'b0100: result = in1&in2; //AND
4'b0101: result = in1^in2; //XOR
4'b0110: result = in1|in2; //OR
4'b0111: result = /*((2^16)-1)-in1;*/(-(in1))-1; //complement
4'b1001: result = in1-1; //decrement
4'b1000: result = in1+1; //increment
endcase
end
endmodule

Any help and advice would be greatly appreciated.

Answer 1

It should work with 4'b1000 etc in if statements. You have just used 1000