Verilog code is compiled but there is no "vcdplus.vpd" waveform file being created when using "$vcdpluson" - FSM Sequence Dectector

Question

My verilog code for my Finite State Machine - Moore (Non-Overlapping) - Sequence detector is not generating a "vcdplus.vpd" waveform file after I have compiled. I'm compiling my verilog code with vcs -debug-access+all <module name>. After that I run a ./simv simulation report.

For my previous verilog codes, I was able to see a "vcdplus.vpd" file with my other files. What could be my issue? I'm sure its right under my nose but I've spent too much time on this and would appreciate any help or advice. I've ran clean compiles (removed all files) twice and even made a new directory. Same unwanted results. I'm using Mobaxterm SSH if that makes a difference, not Xilinx/Vivado (can't use that for this course). My code & testbench are below:

module fsm (clock, reset, x, z);

        input clock;
        input reset;
        input x;
        output reg z;

        parameter s0=4'b0000;
        parameter s1=4'b0001;
        parameter s2=4'b0010;
        parameter s3=4'b0011;
        parameter s4=4'b0100;
        parameter s5=4'b0101;

        reg [3:0] current_state, next_state;

        always @(posedge clock or negedge reset) begin 
        if(reset==1)
                current_state <= s0;
        else
                current_state <= next_state;
        end


        always @(current_state,x)   
        begin
                case(current_state)
                s0: begin
                        if(x==0)
                                next_state <= s0;
                        else
                                next_state <= s1;
                end

                s1: begin
                        if(x==0)
                                next_state <= s2;
                        else
                                next_state <= s1;
                end

                s2: begin
                        if(x==0)
                                next_state <= s3;
                        else
                                next_state <= s1;
                end

                s3: begin
                        if(x==0)
                                next_state <= s0;
                        else
                                next_state <= s4;
                end

                s4: begin
                        if(x==0)
                                next_state <= s2;
                        else
                                next_state <= s5;
                end

                s5: begin
                        if(x==0)
                                next_state <= s0;
                        else
                                next_state <= s1;
                end
                endcase

        end

        always @(current_state)
        begin
                case(current_state)
                s0: z <= 0;
                s1: z <= 0;
                s2: z <= 0;
                s3: z <= 0;
                s4: z <= 0;
                s5: z <= 1;
                default: z <= 0;
                endcase
        end

endmodule

`include "fsm_moore.v"

module fsm_moore_tb;

        reg clock;
        reg reset;
        reg x;

        wire [3:0] z;

        fsm_moore_tb uut( .clock(clock), .reset(reset), .x(x), .z(z));


        initial begin
        $vcdpluson;
                        clock = 1'b0;
                        reset = 1'b1;
                        #15 reset = 1'b0;
                end

        forever #5 clock = ~ clock;


        initial begin

                        #12 x=0;#10 x=1;#10 x=1;#10 x=0;
                        #12 x=0;#10 x=0;#10 x=1;#10 x=0;
                        #12 x=1;#10 x=0;#10 x=0;#10 x=1;
                        #12 x=1;#10 x=1;#10 x=1;#10 x=1;
                        #12 x=0;#10 x=1;#10 x=0;#10 x=0;
                        #10 $finish;

                end

endmodule

Any help is appreciated.

Answer 1

The code you provided cannot be compiled at all. It contains two errors:

1. the forever statement in the fsm_moore_tb module is outside of any procedural block, which is illegal. initial forever #5 clock = ~ clock; would fix the issue.
2. you recursively instantiate module fsm_moore_tb inside the same module. This is illegal. I guess, you need to instantiate fsm: fsm uut( .clock(clock), .reset(reset), .x(x), .z(z));

After fixing both errors, -debug_all (or some other debug qaul) will allow you to use vpd traces.