Verilog linting tools?

Question

What are some good linting tools for verilog? I'd prefer one that can be configured to either handle or ignore certain vendor specific primitives like LUT's, PLL's, etc.

I recently tried verilator-3.810, but out of the box it needs a little help with the primitives.

So what (linting) tools do you use to deal with the not-so-strict syntax of verilog?

Answer 1

Ascent Lint from Real Intent is pretty good. It runs fast and is easy to set up.

Answer 2

I also have used Spyglass and, like toolic indicated, it requires setting up a run script just to check even one file and the default checks complain about useless things like unloaded bits on array data types. Conformal will also output quite a bit of detail for its RTL warnings and you would have to have certain modules excluded anyway, if Formal Verification is part of your flow. Like Spyglass it requires a bit of setup.

Despite having access to these tools I only use them at the very end. During coding and validation I use VCS with lint checks turned on, and fix anything Verdi complains about. This catches quite a bit and does not require any configuration/script files to use. Neither are free(or cheap).

Answer 3

In my experience, it's generally not worth it. Anything I've tried needs loads of initial setup because out-of-the-box they try to check everything. But each shop has it's own coding standards - so you spend loads of time seasoning the linter to taste. Then once you try to integrate IP or code from another section of the company (which generally have a different idea of nice code), the linter goes mental, so you end up saying, wire im_happy = Verdi_happy & simulator_happy & synth_happy;

Answer 4

I have never used a free linting tool, such as the one you mentioned (verilator).

My only experience has been with (expensive) commercial linting tools. Thus far, every one I have used has required me to spend time to customize the rule-set to filter out checks which I consider unimportant. For example, by default, every tool generates many warnings related to signal naming conventions. Since these in no way affect how RTL is synthesized to gates or lead to simulation issues, I choose to disable them.

The Spyglass tool (Atrenta) seems to have the widest range of capabilities, but also requires quite a bit of set-up. I like the Hal tool (Cadence) because it is very easy to start using right away (but, it too requires some set-up).