verilog mux on clock edge

Question

How do I use clock edge as selector for a mux, what I want to do:

input clk, in1, in2;
output out;
always@ (posedge clk) begin out<=in1; end
always@(negedge clk) begin out<=in2; end

however, this is not synthesisable because of multiple drivers in separate always blocks. Is there any work around?

Answer 1

This should get you what you want. Whether it is a good idea or not depends on what you are doing.

input clk, in1, in2;
output out;
assign out = clk ? in1 : in2;

Answer 2

Like so:

module mux1_2(input clk, d0, d1,
              input sel,
              output reg y);

    always@(posedge clk)
    begin
        case(sel)
            1'b0:    y <= d0;
            1'b1:    y <= d1;
        endcase
    end

endmodule

However, you should follow the advice of the others. Multiplexers are very basic combinational devices, I don't see any situation where you would need to place a clock on it.

Answer 3

As others mentioned, using clock as data is not common. A combinational mux be achieved using dwikle's answer, but if you really want to end up with flops (in that case out should be of type reg or logic, which is missing in your original code), then you can write:

always@(edge clk) 
begin
    unique case(clk)
        1'b0:    out <= in1;
        1'b1:    out <= in2;
    endcase
end

or equivalently you could use @(negedge clk or posedge clk) instead of edge. This may however, confuse your synthesis tool. Probably, the following is more straightforward:

always@(posedge clk) 
    out1 <= in1;
always@(negedge clk) 
    out2 <= in2;
assign out = clk ? out1 : out2;