Verilog Testbench Implementation

Question

I'm trying to implement a verilog program and the majority of the test cases are passing (1,188 out of 1440). My question however is that my expected overflow output is currently being displayed at 0 while the expected value is supposed to be 1.

Heres two examples of what's being printed to the logs with the expected value being incorrect (scroll all the way to the right):

in1=1000000000000000 in2=1000000000000000 opCode=1001 result= 0111111111111111  expectedResult= 0111111111111111     overflow=0 expectedOverflow=1 in1=-32768           in2=-32768           opCode= 9 result=  32767            expectedResult=  32767               overflow=0  expectedOverflow=1

in1=1000000000000000 in2=1000000000000001 opCode=1001 result= 0111111111111111  expectedResult= 0111111111111111     overflow=0 expectedOverflow=1 in1=-32768           in2=-32767           opCode= 9 result=  32767            expectedResult=  32767               overflow=0  expectedOverflow=1

I can't find exactly where I went wrong with my implementation. So I guess my question is, what exactly did I do wrong? Thanks!

Heres an implementation of my verilog code for reference:

module Calculator(in1,in2,opCode,result,overflow);

input signed[15:0] in1, in2;

input[3:0] opCode;  
output reg signed[15:0] result;
output reg overflow;

always @ (*) begin
if(opCode == 0000) begin
   if(in1+in2<=32767 & in1+in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0001) begin
   if(in1-in2<=32767 & in1-in2>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0010) begin
   if(in1*5<=32767 & in1*5>= -32768) begin
       overflow = 0;
       end
       else
       begin
       overflow = 1;
       end
       end
end

always @ (*) begin
   if(opCode == 0011) begin
   if ((in1 % 10) == 0) begin
   overflow = 0;
end else begin
   overflow = 1;
end
   end
end

always @ (*) begin
   if(opCode == 0100) begin
   overflow = 0;
       end
end

always @ (*) begin
if(opCode == 0101) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 0110) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 0111) begin
   overflow = 0;
       end
end

always @ (*) begin
   if(opCode == 1000) begin
   if(in1 == 32767) begin
       overflow = 1;
       end
       else begin
       overflow = 0;
       end
       end
end

always @ (*) begin
   if(opCode == 1001) begin
   if(in1==-32768) begin
       overflow = 1;
       end
       else
       begin
       overflow = 0;
       end
       end
end

always @ (*) begin
case(opCode)
4'b0000: result = in1+in2; //add
4'b0001: result = in1-in2; //subtract
4'b0010: result = in1*5; //mult by 5
4'b0011: result = in1/10; //divide by 10
4'b0100: result = in1&in2; //AND
4'b0101: result = in1^in2; //XOR
4'b0110: result = in1|in2; //OR
4'b0111: result = /*((2^16)-1)-in1;*/(-(in1))-1; //complement
4'b1001: result = in1-1; //decrement
4'b1000: result = in1+1; //increment
endcase
end

endmodule

Answer 1

Reassigning the same variable will result in such errors. Try adding new variables/registers for your code and you can aslo remove the "always@*"(in every if case) and just use "begin . . . end" format inside a single program. Provided you "begin" initially and "end" finally it will work fine.